[Dsg-rich] Third cable and connector on RICH LV boards' service connector

[Valery Kubarovsky]

Hi All, 

To simplify the interlock system I suggest to use the CAEN mainframe interlock input. 
The sequence of shutting off HV and LV that we discussed before is not mandatory. 

regards, 
Valery 

> From: "Tyler Lemon" <tlemon at jlab.org>
> To: "Chris Cuevas" <cuevas at jlab.org>
> Cc: "dsg-rich" <dsg-rich at jlab.org>, "Benjamin Raydo" <braydo at jlab.org>
> Sent: Wednesday, August 9, 2017 4:10:46 PM
> Subject: Re: [Dsg-rich] Third cable and connector on RICH LV boards' service
> connector

> Hello Chris,

> My reply is inline below in blue.

> Hi,

> If the 'hardware interlock system' produces an interlock relay closure, and this
> closure is the logical OR of several signals, then the closure should be
> connected to the CAEN mainframe interlock input(CPU). Is this the case?

> For the LV boards, the hardware interlock system will open a relay to break the
> short circuits required at the service connector to enable a group's output.
> This is described in on page 7 of the attached manual for the A2518 boards.

> We are not using the interlock input on the CAEN mainframe because when asked,
> Valery said HV should be turned off before LV. Using the interlock input on the
> mainframe will shutoff both HV and LV at the same time.

> The interlock signals on the A2518 boards control two groups of 4 low voltage
> outputs. Each output channel has over-voltage and over-current trip points,

> We are not monitoring any current or voltage output of HV or LV. The hardware
> interlock system will only disable HV/LV in the event that one of the hardware
> interlock system sensors (temperature, humidity, N2 flow, cooling airflow,
> cooling tank pressure) goes out of the determined limits.

> and I do not see the need to interface to each group of LV interlocks if there
> is a global interlock signal that will latch a disable condition.

> We have programed the hardware interlock system in a way that disables all LV
> groups at once and all HV channels at once. The hardware interlock system does
> not disable/enable each individual group.

> Is it really necessary to sequence the shutoff of HV and LV?
> If not, we can change the hardware interlock system code to use the CAEN
> mainframe interlock input.

> Best regards,
> Tyler

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