[Dsg-rich] HV/LV sequencing for RICH hardware interlocks

[Amrit Yegneswaran]

exceptional tyler, simply exceptional. 
crystal clear status and phenomenal record keeping. 
i like the meeting minutes, you attached. 
the student is the master now! 

so, the fiasco of Chianti i was consuming wasn't making me remember things that hadn't happened. 
but then again, I prefer to not remember things that happened. 
hmm! what a fiasco! 

From: "Tyler Lemon" <tlemon at jlab.org> 
To: "dsg-rich" <dsg-rich at jlab.org> 
Sent: Thursday, August 10, 2017 11:51:38 AM 
Subject: [Dsg-rich] HV/LV sequencing for RICH hardware interlocks 

Hello Marco, 

As we discussed in the meeting this morning, we will interlock the RICH HV and LV using the CAEN mainframe interlock input. HV and LV disable sequencing can be added at later time as the required cable modifications will take time. 

To implement HV/LV sequencing, it would take one week . 
The LV cables need to be modified to add a daisy chain that allows only LV boards to be enabled/disabled. The circuit diagrams for the daisy chain were given to DSG by CAEN. 
After cable modifications, the cables and daisy chains will need to be tested. 
The programming required to sequence HV and LV shutoff is already complete at the request of Valery in the June 20, 2017 meeting (see point 5.3 in attached minutes from June 20 meeting) . 

To implement the interlocks using the CAEN mainframe interlock input, it will take one day . 
The appropriate cable and connectors are on hand. 
The programming changes required to remove the already developed HV/LV sequencing can be done by the end of today. 

HV and LV sequencing will be removed from the Hardware Interlock System LabVIEW code and the logic will be re-added to implement HV/LV interlocks using the CAEN interlock input. 

Regards, 
Tyler 


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