[Dsg-rich] RICH alarm

[Benjamin Raydo]

Hi Marco,

Attached is EPICS plot of B_DAQ:coda_status

You can see that the current drop coincides with a DAQ restart. When RICH is configured the power does drop as many peripherals are not running in the RICH FPGA modules. Probably the alarm threshold should be lowered since it is a false alarm/concern.

Ben


----- Original Message -----
From: "Mirazita Marco" <Marco.Mirazita at lnf.infn.it>
To: dsg-rich at jlab.org
Sent: Tuesday, November 20, 2018 12:26:49 PM
Subject: [Dsg-rich] RICH alarm

Hi all,
tonight at 3:39:45 we had an alarm on the RICH electronics, see log 
entry https://logbooks.jlab.org/entry/3628796.
The alarm was self-cleared and was too fast to allow the people in shift 
to understand more than what came out from the alarm screen. No effect 
on the data was reported.
I made some investigation and the only possible indication of some 
problem is a slight decrease in the LV monitored current by about 0.1 A 
occurred around 3:34 and recovered at around 3:40, see first picture.
However, events like that seems to be quite common (see second picture) 
and we never get any alarm.
So, the cause of the alarm remains unclear but most likely is not an 
issue.
Best regards,
Marco


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