[Dsg-rich] RICH airflow tests?

[Valery Kubarovsky]

Hello Tyler, 

I replied to your mail where you presented the plan to test RICH cooling system: 

========== 
The general procedure in the study would be: 
1.) turn on HV/LV and let the EP reach its normal running temperature. 
2..) decrease airflow to set values (decrease in ~50 slm increments?). 
3.) Allow RICH to reach a steady temperature after change. 
4.) Repeat steps 2 and 3 until FPGA temperatures reach some upper limit (maybe 75 deg C?) 
=========== 

If you have another plan with HV/LN OFF you can do it. THE CLAS DAQ may be busy so you have to inform Sergey Boiarinov that RICH electronics will not be available for DAQ. 

Regards, 
Valery 

> From: "Tyler Lemon" <tlemon at jlab.org>
> To: "Valery Kubarovsky" <vpk at jlab.org>
> Cc: "dsg-rich" <dsg-rich at jlab.org>
> Sent: Wednesday, September 5, 2018 4:25:07 PM
> Subject: Re: [Dsg-rich] RICH airflow tests?

> Hello Valery,

> We will not plan to perform any tests where the airflow is changed while
> electronics are on.

> However, there is one short test that would be good to do during this downtime
> with all electronics powered off. We have not tested whether the current air
> cooling set up can provide enough air cooling for two RICH sectors. To test
> this, we would turn all electronics off, temporarily reconfigure the
> air-cooling valve panel to supply 900 slm to RICH from one of its outputs, and
> then see if we can also get an additional 900 slm from the second output on the
> panel.

> This test shouldn't take too long, maybe an hour at most. The air-cooling panel
> will be reconfigured how it is now (500 slm on Airflow 1 and 400 slm on Airflow
> 2) at the conclusion of the test.

> Best regards,
> Tyler

> From: "Valery Kubarovsky" <vpk at jlab.org>
> To: "Tyler Lemon" <tlemon at jlab.org>
> Cc: "dsg-rich" <dsg-rich at jlab.org>
> Sent: Wednesday, September 5, 2018 3:08:23 PM
> Subject: Re: [Dsg-rich] RICH airflow tests?

> Hello Tyler,

> For a moment right now the maximum FPGA temperature is 65F. HV is OFF. Expect
> higher t when HV will be ON.
> The limit is coming not only from the electronics itself but from the melting
> temperature of the fiber-optics cable that just touches
> the FPGA chip. The temperature that we have now is almost at the limit. I am not
> in favor to make any test that will increase the electronics panel t.

> I suggest another study that will help us to understand setting for the high
> limit temperature of your sensors.
> For a moment the difference between current t and high limit is around 5
> degrees. If we will study the
> t fluctuation with time of all 16 sensors we can decrease probably this limit
> and get more safe run conditions.
> We can study this behavior using spring data or take new one right now with HV
> ON.

> Best regards,
> Valery

>> From: "Tyler Lemon" <tlemon at jlab.org>
>> To: "dsg-rich" <dsg-rich at jlab.org>
>> Sent: Wednesday, September 5, 2018 2:42:17 PM
>> Subject: [Dsg-rich] RICH airflow tests?

>> Hello Marco and Valery,

>> A few months ago, you mentioned that it'd be good to figure out more precisely
>> what airflow is needed to keep RICH electronics cool.

>> Since there will not be beam and Hall B will be open until next week, would we
>> be able to run tests this week to determine how changes in cooling airflow
>> affect RICH FPGA temperatures and hardware interlock RTDs?

>> The general procedure in the study would be:
>> 1.) turn on HV/LV and let the EP reach its normal running temperature.
>> 2..) decrease airflow to set values (decrease in ~50 slm increments?).
>> 3.) Allow RICH to reach a steady temperature after change.
>> 4.) Repeat steps 2 and 3 until FPGA temperatures reach some upper limit (maybe
>> 75 deg C?)

>> The tests would also allow better limits on the hardware interlock to be set
>> because we would have data supporting at what airflow RICH electronics
>> temperatures start to get too high.

>> Please let us know.

>> Best regards,
>> Tyler

>> _______________________________________________
>> Dsg-rich mailing list
>> Dsg-rich at jlab.org
>> https://mailman.jlab.org/mailman/listinfo/dsg-rich
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