[Dsg-rich] [EXTERNAL] RICH electronics
Tomassini Sandro
sandro.tomassini at lnf.infn.it
Mon Sep 30 16:00:38 EDT 2019
Hi Tyler,
I agree with you and Vincenzo that this is a good idea.
I also like what George suggested to increase heat dissipation for the new epanel.
Many thanks
Sandro
Inviato da BlueMail
Il giorno 30 set 2019, 13:52, alle ore 13:52, Tyler Lemon <tlemon at jlab.org> ha scritto:
>Hi Vincenzo,
>
>That is correct, we are looking into some sort of chiller. Since the
>flow rates for RICH cooling are so high, we considering the possibility
>that this system may need to be designed from scratch to be able to
>meet the requirements in what RICH needs.
>
>We will also take into consideration the possibility of condensation on
>the piping as a result of cooling the air.
>
>Best regards,
>Tyler
>________________________________
>From: Vincenzo Lucherini <Vincenzo.Lucherini at lnf.infn.it>
>Sent: Monday, September 30, 2019 3:22 AM
>To: Tyler Lemon <tlemon at jlab.org>
>Cc: George Jacobs <jacobsg at jlab.org>; Tomassini Sandro
><sandro.tomassini at lnf.infn.it>; dsg-rich at jlab.org <dsg-rich at jlab.org>
>Subject: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>
>do you mean to insert a "chiller"?
>That would be a good thing, but one must carefully study it in order to
>avoid any condensation of water vapor in the piping inside the
>Electronic Panel.
>
>Il 2019-09-27 20:25 Tyler Lemon ha scritto:
>> Hi Sandro,
>>
>> In addition to what George mentioned, DSG is also looking into the
>> concept of an externally-cooled compressor system that would be able
>> to provide cooled air to RICH, increasing the current compressors'
>> cooling capabilities. Depending on what we find, such a system may
>> allow us to cool two RICH sectors with one compressor.
>>
>> Once we have any other information on how this could be done, we
>will
>> distribute the info to the RICH collaboration.
>>
>> Best regards,
>> Tyler
>>
>> -------------------------
>>
>> FROM: Dsg-rich <dsg-rich-bounces at jlab.org> on behalf of George Jacobs
>> <jacobsg at jlab.org>
>> SENT: Friday, September 27, 2019 1:37 PM
>> TO: Tomassini Sandro <sandro.tomassini at lnf.infn.it>;
>> dsg-rich at jlab.org <dsg-rich at jlab.org>
>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>
>> Hi Sandro,
>>
>> If I remember correctly, each line is currenly supplied by it's own
>> rotameter. So, if you want to do this, you must contact the Hall B
>> Engineer. He is the system owner. He is in charge of the system. You
>> may or may not need a TOSP for this, but that is up to Hall B.
>>
>> There are other things you can do to improve cooling efficiency. For
>> example, cable routing inside the e-panel should be improved in the
>> next RICH sector. Another, would be exploring the use of finned
>> plastic heat sinks on the components to increase the surface area to
>> be cooled.
>>
>> Cheers,
>> George
>>
>> --
>> George Jacobs
>> Jefferson Lab (TJNAF)
>> STE 12
>> 12000 Jefferson Ave.
>> Newport News, VA 23606
>> (office) 757-269-7021
>> (email) jacobsg at jlab.org
>>
>> -------------------------
>>
>> FROM: Dsg-rich <dsg-rich-bounces at jlab.org> on behalf of Tomassini
>> Sandro <sandro.tomassini at lnf.infn.it>
>> SENT: Friday, September 27, 2019 5:03 AM
>> TO: dsg-rich at jlab.org <dsg-rich at jlab.org>
>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>
>> Hi All,
>> inside the rich e-panel there are two air manifolds but I do not
>> remember if we have the possibility to adjust the flow separately.
>> What might be interesting to test is to change the flow in the two
>> manifolds separately in order to find the best setup that minimizes
>> the flow towards the detector keeping a good safety margin on the max
>> temperatures on the electronic boards.
>> May be I am dreaming...
>> George is this possible in your opinion?
>> Hope to see you soon
>>
>> Many thanks
>>
>> Sandro
>>
>> Il 24/09/2019 14:23, Tyler Lemon ha scritto:
>>
>>> Hello,
>>>
>>> From Ben and Mateo's reply, it seems the goal of the test should be
>>> to keep the same temperatures in RICH as previous running periods.
>>>
>>> Ideally, the test would involve finding what airflow settings are
>>> required to maintain ~65 C in RICH FPGAs. It may be that 900 slm is
>>> actually required to keep temperatures in the appropriate range.
>>>
>>> At a bare minimum, the tests should involve adjusting compressor
>>> settings with the goal of maintaining 900 slm total flow. For this,
>>> RICH electronics can be left off since the airflow measurements
>>> would be the indicator of test results.
>>>
>>> It is as Marco said, we never tried to optimize the cooling system.
>>> These tests would be the only way to see what is actually needed to
>>> cool RICH and to see whether the current cooling system could even
>>> provide enough flow for two RICH sectors.
>>>
>>> - Tyler
>>>
>>> -------------------------
>>>
>>> FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>> SENT: Tuesday, September 24, 2019 4:18 AM
>>> TO: Amrit Yegneswaran <yeg at jlab.org>
>>> CC: Benjamin Raydo <braydo at jlab.org>; Tyler Lemon
>>> <tlemon at jlab.org>; dsg-rich <dsg-rich at jlab.org>
>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>
>>> Hi all,
>>> let me make a couple of remarks.
>>>
>>> 1) The temperature limits were set to ensure a safe operation of
>>> the
>>> whole system, which, as Ben said, includes not just the FPGA, but
>>> cables, MAROC, external temperature close to TOF, etc. I don't want
>>> to
>>> change these limits unless strictly necessary and only if with no
>>> risk
>>> for the detectors.
>>> However, we know that the current running conditions are mostly
>>> driven
>>> by one FPGA which is producing more heat (its temperature is about
>>> 2 or
>>> 3 degrees higher than the neighbors) and by chance it is also in
>>> the
>>> hottest spot of the panel.
>>>
>>> 2) The cooling system was originally designed to be able to feed
>>> two
>>> RICH modules with one compressor, in case of failure of the other
>>> one.
>>> We are now far from this situation. We run one RICH with 900 slm
>>> with a
>>> maximum of 1200 slm per compressor. But we never attempted a real
>>> optimization of the air flow. For example, the lower line is
>>> flowing
>>> less air than the upper one, while I would expect the opposite.
>>>
>>> For these reasons, I think there could be room to optimize the
>>> running
>>> conditions and get closer to the original design.
>>> But let me stress again that this optimization must ensure to stay
>>> within the safety limits.
>>>
>>> Best regards,
>>> Marco
>>>
>>> Il 2019-09-24 04:12 Amrit Yegneswaran ha scritto:
>>>> given ben's last sentence
>>>>
>>>> (highlighted; i guess "it" in the sentence refers to "the
>>>> temperature" as does "that".
>>>> from which we have it = that => i = hat or i =tha, aah the
>>> pronouns
>>>> they are precious!)
>>>>
>>>> anyway i'm now very confused about the planned test and the
>>> intent
>>>> thereof?
>>>>
>>>> are we thinking reducing the airflow from ~950 slm will reduce
>>> the
>>>> temperature below 65c?
>>>> pardon my obtuseness.
>>>>
>>>> so what mods are you conjuring up tyler?
>>>>
>>>> -------------------------
>>>>
>>>> FROM: Benjamin Raydo <braydo at jlab.org>
>>>> SENT: Monday, September 23, 2019 5:33 PM
>>>> TO: Tyler Lemon <tlemon at jlab.org>; Amrit Yegneswaran
>>> <yeg at jlab.org>;
>>>> Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>>> CC: dsg-rich <dsg-rich at jlab.org>
>>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>>
>>>> Hi Tyler,
>>>>
>>>> Matteo is correct about the temperature limit of 85C to respect
>>> the
>>>> FPGA timing constraints, but we also have fiber cables running
>>> close
>>>> to those parts that are rated for 80C (I'd expect some
>>> deformation
>>>> possible if we go above this for a long period).
>>>>
>>>> Can we set a safe limit of 75C for any reported FPGA temperature
>>> for
>>>> your tests (short term limit: <1hr)? If your tests need to run in
>>> such
>>>> a way that you want a higher limit, let us discuss again if you
>>> don't
>>>> mind. For long term it would be great to keep it as low as
>>> possible
>>>> and for the moment I believe we've been running with the hottest
>>> FPGA
>>>> temp to be around 65C so don't want to see that increase
>>> significantly
>>>> if there are any changes to the cooling.
>>>>
>>>> Hope that helps.
>>>>
>>>> Thanks,
>>>> Ben
>>>>
>>>> -------------------------
>>>>
>>>> FROM: Tyler Lemon <tlemon at jlab.org>
>>>> SENT: Monday, September 23, 2019 4:59 PM
>>>> TO: Amrit Yegneswaran <yeg at jlab.org>; Marco Mirazita
>>>> <Marco.Mirazita at lnf.infn.it>; Benjamin Raydo <braydo at jlab.org>
>>>> CC: dsg-rich <dsg-rich at jlab.org>
>>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>>
>>>> Hi Ben,
>>>>
>>>> In October, we're planning on doing some testing to optimize
>>> RICH's
>>>> cooling system and see what would needed to modify the system to
>>> cool
>>>> two RICH sectors.
>>>>
>>>> With respect to the RICH readout electronics, FPGAs, and their
>>>> timing, are there any temperature limits we should take into
>>>> consideration when testing the cooling system?
>>>>
>>>> Thanks,
>>>> Tyler
>>>>
>>>> -------------------------
>>>>
>>>> FROM: Amrit Yegneswaran <yeg at jlab.org>
>>>> SENT: Monday, September 23, 2019 4:48 PM
>>>> TO: Tyler Lemon <tlemon at jlab.org>; Marco Mirazita
>>>> <Marco.Mirazita at lnf.infn.it>
>>>> CC: dsg-rich <dsg-rich at jlab.org>
>>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>>
>>>> tyler
>>>> address fpga temp issue with ben.
>>>> i believe 60c is right at the edge of timing issues, not sure.
>>>> -------------------------
>>>>
>>>> FROM: Dsg-rich <dsg-rich-bounces at jlab.org> on behalf of Tyler
>>> Lemon
>>>> <tlemon at jlab.org>
>>>> SENT: Monday, September 23, 2019 3:11 PM
>>>> TO: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>>> CC: dsg-rich <dsg-rich at jlab.org>
>>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>>
>>>> Hi Marco,
>>>>
>>>> Looking back at EP temperatures during steady operations (I
>>> picked
>>>> 3/10/2019 to 3/31/2019), Hardware Interlock RTDs were ~40 deg C
>>> and
>>>> FPGA temperatures were ~60 deg C.
>>>>
>>>> Is there a temperature increase that would be considered
>>> acceptable?
>>>> For example if the FPGA temperatures were ~70 deg C rather than
>>> ~60
>>>> deg C?
>>>>
>>>> The first test should be determining what flow rate is actually
>>>> needed to maintain EP temperatures in that acceptable range with
>>> all
>>>> RICH electronics on.
>>>>
>>>> -Tyler
>>>>
>>>> -------------------------
>>>>
>>>> FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>>> SENT: Monday, September 23, 2019 9:01 AM
>>>> TO: Tyler Lemon <tlemon at jlab.org>
>>>> CC: dsg-rich <dsg-rich at jlab.org>
>>>> SUBJECT: Re: [Dsg-rich] [EXTERNAL] RICH electronics
>>>>
>>>> Hi Tyler,
>>>> sorry, I had in mind that the replacement of the PT was scheduled
>>> for
>>>>
>>>> last Wednesday.
>>>>
>>>> The tests we have in mind to optimize the cooling system is
>>> basically
>>>>
>>>> what you said. But we still have to make a plan of the specific
>>>> measurements we need. We will do this plan in the next weeks.
>>>> Any suggestion from you and the DSG is welcome.
>>>>
>>>> Best regards,
>>>> Marco
>>>>
>>>> Il 2019-09-20 20:46 Tyler Lemon ha scritto:
>>>> > Hi Marco,
>>>> >
>>>> > The PT replacement has not been completed. It is scheduled for
>>> next
>>>> > Wednesday September 25.
>>>> >
>>>> > As for the visit to optimize RICH running conditions, I will
>>> not be
>>>> > at work for at least part of the week of October 21 to October
>>> 25,
>>>> > however there should be other people from DSG that would be
>>> able to
>>>> > help.
>>>> >
>>>> > What tests are being planned for the visit? Would it
>>> essentially be
>>>> > varying the settings of the cooling system (flow rate, buffer
>>> tank
>>>> > pressure, compressor output pressure) and seeing how the
>>>> temperature
>>>> > within RICH is affected?
>>>> >
>>>> > Best regards,
>>>> > Tyler
>>>> >
>>>> > -------------------------
>>>> >
>>>> > FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>>> > SENT: Friday, September 20, 2019 12:21 PM
>>>> > TO: Tyler Lemon <tlemon at jlab.org>
>>>> > CC: dsg-rich <dsg-rich at jlab.org>; Valery Kubarovsky
>>> <vpk at jlab.org>;
>>>> > marco contalbrigo <mcontalb at fe.infn.it>
>>>> > SUBJECT: Re: [EXTERNAL] RICH electronics
>>>> >
>>>> > Hi Tyler,
>>>> > do you know if Bob has completed the replacement of the FT?
>>>> > If so, the compressor could be restarted on Monday morning,
>>> once we
>>>> > are
>>>> > sure everything is working properly I can turn on the RICH
>>>> > electronics
>>>> > and keep it on for the night and then make the tests on Tuesday
>>>> > morning.
>>>> >
>>>> > As you know, we didn't have much time to optimize the working
>>> point
>>>> > of
>>>> > the cooling system after the RICH installation, we simply
>>> choose
>>>> > running
>>>> > conditions that ensure a safe operation of the detector.
>>>> > But these running conditions might be problematic with two RICH
>>>> > modules
>>>> > and definitely not sustainable in case of failure of one of the
>>> two
>>>> > compressors.
>>>> > Therefore, also in preparation of the upcoming CLAS12 data
>>> taking,
>>>> > I'm
>>>> > planning a visit to JLab for Dario and Sandro to try to
>>> optimize
>>>> the
>>>> > running conditions, and to be effective this work must be
>>>> coordinated
>>>> >
>>>> > with you and the DSG.
>>>> > The proposed dates are from October 21 to October 31. Is this
>>> plan
>>>> ok
>>>> >
>>>> > for you?
>>>> > Thank you,
>>>> > Marco
>>>> >
>>>> > Il 2019-09-18 14:12 Tyler Lemon ha scritto:
>>>> > > Hi Marco,
>>>> > >
>>>> > > Bob Miller has scheduled the replacement of the faulty
>>> pressure
>>>> > > transducer (PT) on the air-cooling buffer tank for next
>>>> Wednesday,
>>>> > > September 25.
>>>> > >
>>>> > > Could the tests be scheduled to start Thursday September 26?
>>>> > >
>>>> > > Best regards,
>>>> > > Tyler
>>>> > >
>>>> > > -------------------------
>>>> > >
>>>> > > FROM: Marco Mirazita <Marco.Mirazita at lnf.infn.it>
>>>> > > SENT: Wednesday, September 18, 2019 4:08 AM
>>>> > > TO: Tyler Lemon <tlemon at jlab.org>
>>>> > > CC: dsg-rich <dsg-rich at jlab.org>; Valery Kubarovsky
>>>> <vpk at jlab.org>;
>>>> > > marco contalbrigo <mcontalb at fe.infn.it>
>>>> > > SUBJECT: [EXTERNAL] RICH electronics
>>>> > >
>>>> > > Hi Tyler,
>>>> > > the RICH electronics is off since quite a lot of time and in
>>>> > > preparation
>>>> > > of the upcoming CLAS12 running I would like to turn it on to
>>>> verify
>>>> > > that
>>>> > > everything is still working and eventually to take new scaler
>>>> > > calibration data.
>>>> > > I could plan this work for the beginning of the next week.
>>>> > > In preparation for that, we should coordinate to have all the
>>>> > systems
>>>> > >
>>>> > > ready. Would you be available to start the compressor for the
>>>> test?
>>>> > > Thank you,
>>>> > > Marco
>>>> >
>>>> > _______________________________________________
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>>>>
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>>
>> --
>> -----------------------------------------
>> Dr. Eng. Sandro Tomassini
>> Istituto Nazionale di Fisica Nucleare
>> Laboratori Nazionali di Frascati
>> ---Research Division---
>> P.O.Box 13 00044 Frascati (RM) Italy
>> Tel. office: +39 06 9403 2919/8089
>> Fax: +39 06 94032256
>> e-mail: sandro.tomassini at lnf.infn.it
>>
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