[Dsg-hallc_controls] Revised routine

[Amanda Hoebel]

Hi Mike,


I am unsure of how to export routines to .L5X from version 16 of RSLogix 5000 (since this is for HMS), or if that can even be done.  I know it can be done in version 20.  Attached is the .csv file of the tag names and the ACD file which you could use to copy/paste the routines into the program.


Regards,

Amanda

________________________________
From: Steven Lassiter
Sent: Friday, January 4, 2019 10:39 AM
To: Amanda Hoebel
Subject: Re: Revised routine


Hello Amanda,


 can you send me the routines (*.L5x) and tags (*.csv) (controller vs program, names and type) in a separate file.

I will load into the test PLC and test it out


thanks

Steven

________________________________
From: Dsg-hallc_controls <dsg-hallc_controls-bounces at jlab.org> on behalf of Amanda Hoebel <amandah at jlab.org>
Sent: Wednesday, November 28, 2018 3:27:16 PM
To: dsg-hallc_controls at jlab.org
Subject: [Dsg-hallc_controls] Revised routine

Hi Mike,

Attached are the PDFs of the revised function block diagrams and ladder logic.

Regards,
Amanda


________________________________
From: "Mike Fowler" <fowler at jlab.org>
To: "dsg-hallc controls" <dsg-hallc_controls at jlab.org>
Sent: Monday, November 12, 2018 8:43:23 AM
Subject: Re: [Dsg-hallc_controls] DSG's PLC tasks report

>>>DSG's weekly report
>>>Modified to PLC routine to ramp down the quadrupoles when interlock is enabled
(PSU_Sum_Interlock bit =1).
Not required. The existing PLC code ramps down the power supply when there is an interlock.

>>>>Added pulse-timer that waits for 100 ms and then transmits trigger pulse to enable the sending of
0 A current value.
Not required.

The new current regulation code should go into standby waiting for new input.
The code should not try to control the power supply when/if there is an interlock.

Cheers,
Mike




On 11/9/2018 4:56 PM, Pablo Campero wrote:
Hello,

I have attached the DSG's weekly report for Hall C-PLC tasks.

Best Regards,
Pablo



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