[Dsg-rich] Fwd: RICH HV/LV board interlock testing

[Chris Cuevas]

Hi Valery,

We have received the CAEN HV modules and a few of the LV modules.

The new CAEN mainframe will be delivered this week.(hopefully).

We will fabricate a LV cable set including the sense line that will 
ultimately be used in the Hall. This cable set will provide
LV power for thirty-two(32) 'tiles' and will be the length determined by 
Bob Miller.

As soon as we receive the mainframe, we can move it to the EEL clean 
room for initial testing. How does the cRIO hardware interlock system
connect/control the HV, LV modules? Is it simply a closure to the CAEN 
mainframe CPU module(A4528) front panel interlock input?

-Chris
~~~~~~~~~~~~~~~~~~

On 7/31/2017 10:47 AM, Valery Kubarovsky wrote:
> Chris,
> DSG wants to test RICH HV and LV  interlock.
> Could we install everything that we have in the EEL building clean room?
> Regards,
> Valery
>
> ------------------------------------------------------------------------
> *From: *"Tyler Lemon" <tlemon at jlab.org>
> *To: *"dsg-rich" <dsg-rich at jlab.org>
> *Sent: *Monday, July 31, 2017 8:17:07 AM
> *Subject: *[Dsg-rich] RICH HV/LV board interlock testing
>
> Hello Valery,
>
> We need to test the interlock enable ability of RICH HV and LV boards 
> to be able to fully complete the cRIO-based hardware interlock system.
>
> Marco Contalbrigo mentioned that the power supplies would be moved 
> soon to start installing the electronics on the electronic panel.
>
> Could we install all HV and LV boards in the power supply mainframe to 
> be able to test the interlock enable functions?
>
> Best regards,
> Tyler
>
>
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